The present invention relates to integrated circuits and, more particularly, to semiconductor-on-insulator transistors. A major objective of the present invention is to provide improved silicon-on-insulator transistors that are capable of high-speed operation and resistant to damage by electrostatic discharge.
Much of modern progress is associated with the increasing circuit density and speeds of integrated circuits. One type of transistor, the insulated-gate field-effect transistor (IGFET) has provided for particularly favorable specifications for circuit density, performance, and power consumption and dissipation. IGFETs are more commonly known as MOS transistors. "MOS" stands for "metal oxide silicon"; however, in modern devices, the "metal" is doped polysilicon.
MOS transistors include a source, a drain, a channel, and a gate. The source and drain are semiconductor (typically silicon) regions doped so that they have a common conductivity type. An NMOS transistor has an n-type source and an n-type drain, while a PMOS transistor has a p-type source and a p-type drain. In an n-type semiconductor region, electrons are the majority charge carriers, while in a p-type semiconductor region, holes are the majority charge carriers. The source and drain are separated by a channel. Conduction between the source and drain is controlled by a field applied to the channel, which in turn results from a voltage applied to the gate. The gate is separated and insulated from the channel by an oxide insulator.
The conductivity type of channels of enhancement-mode MOS transistors is opposite that of the source and drain in the absence of a gate-to-source bias. Applying a suitable voltage to the gate creates an inversion layer in the channel. The inversion layer has the same conductivity type as the source and drain. Thus, the inversion layer conducts while the gate is applied and the inversion layer is in place. Such enhancement-mode MOS transistors are far more common than the alternative depletion-mode MOS transistors. In the absence of a gate-to-source voltage, the channel of a depletion-mode transistor has the same conductivity type as the source and drain so that it conducts. A suitable gate voltage depletes the channel of carriers, turning the transistor off.
One of the obstacles to greater circuit speeds is imposed by parasitic capacitances that afflict bulk silicon integrated circuits. In a conventional bulk silicon integrated circuit, transistor sources, drains, and channels are defined by doping regions of a silicon substrate. The boundaries of the source/drain regions with surrounding substrate silicon typically define diode junctions that have associated junction capacitances. The capacitances resist changes in gate voltages and transistor currents, thus impairing the switching speed of the transistors.
Silicon-on-insulator (SOI) technology provides for faster switching rates by eliminating non-functional junctions in the substrate. The silicon in which devices are defined is insulated from the substrate (which can be of silicon) by an insulating layer of, for example, silicon dioxide. Thus, source/drain active regions are bounded from below by insulator rather than by silicon of an opposite conductivity type. The insulator boundary does not produce parasitic capacitance so that faster transistor switching can occur.
When gate voltage changes are not significantly limited by parasitic capacitances, the sensitivity with which the channel responds to gate voltage changes can become a limiting factor. This sensitivity is maximized by making the silicon layer thin enough that substantially the entire depth of the channel region can be depleted by an appropriate gate voltage. Full depletion maximizes transistor switching speeds.
SOI circuits have thus been formed at high densities and with high operating speeds. Unfortunately, such circuits have been relatively vulnerable to electrostatic discharge. In particular, SOI transistors used for interfacing with external components can be exposed to electrostatic discharge; when so exposed, the transistors can be impaired or destroyed. While precautions can be used to limit such exposure, it would be highly desirable to make SOI transistors that can better withstand such exposure, yet maintain the high speed operation associated with SOI transistor circuits.